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| CMT60N03 N-CHANNEL Logic Level Power MOSFET APPLICATION Buck Converter High Side Switch Other Applications VDSS 30V RDS(ON) Typ. 10.8m ID 50A FEATURES Low ON Resistance Low Gate Charge Peak Current vs Pulse Width Curve Inductive Switching Curves Improved UIS Ruggedness PIN CONFIGURATION TO-252 TO-263 SYMBOL D Front View Front View D SOURCE DRAIN GATE G 1 2 3 S G 1 2 3 S N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS Rating Drain to Source Voltage (Note 1) Drain to Current Continuous Tc = 25J , VGS@10V (Note 2) Continuous Tc = 100J , VGS@10V (Note 2) Pulsed Tc = 25J , VGS@10V (Note 3) Continue Symbol VDSS ID ID IDM VGS PD dv/dt TJ, TSTG EAS TL TPKG IAS Value 30 50 Fig.3 Fig.6 20 52 0.5 3.0 -55 to 150 500 300 260 Fig.8 V W W/J V/ns J mJ J J Unit V A Gate-to-Source Voltage Total Power Dissipation Derating Factor above 25J Peak Diode Recovery dv/dt (Note 4) Operating Junction and Storage Temperature Range Single Pulse Avalanche Energy L=1.1mH,ID=30 Amps Maximum Lead Temperature for Soldering Purposes Maximum Package Body for 10 seconds Pulsed Avalanche Rating THERMAL RESISTANCE Symbol RJC RJA RJA Parameter Junction-to-case Junction-to-ambient (PCB Mount) Junction-to-ambient Min Typ Max 2.4 50 62 Units J /W J /W J /W Test Conditions Water cooled heatsink, PD adjusted for a peak junction temperature of +150J Minimum pad area, 2-oz copper, FR-4 circuit board, double sided 1 cubic foot chamber, free air 2004/05/24 Preliminary Champion Microelectronic Corporation Page 1 CMT60N03 N-CHANNEL Logic Level Power MOSFET ORDERING INFORMATION Part Number CMT60N03N252 CMT60N03N263 Package TO-252 TO-263 ELECTRICAL CHARACTERISTICS Unless otherwise specified, TJ = 25J . CMT60N03 Characteristic OFF Characteristics Drain-to-Source Breakdown Voltage (VGS = 0 V, ID = 250 g A) Breakdown Voltage Temperature Coefficient, Fig.11 (Reference to 25J , ID = 250 g A) Drain-to-Source Leakage Current (VDS = 24 V, VGS = 0 V, TJ = 25J ) (VDS = 24 V, VGS = 0 V, TJ = 125J ) Gate-to-Source Forward Leakage (VGS = 20 V) Gate-to-Source Reverse Leakage (VGS = -20 V) ON Characteristics Gate Threshold Voltage,Fig.12 (VDS = VGS, ID = 250 g A) Static Drain-to-Source On-Resistance, Fig.9,10 (VGS = 10 V, ID = 15A) (VGS = 4.5 V, ID = 12A) Forward Transconductance (VDS = 15 V, ID = 12A) Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge (VGS = 10 V) Total Gate Charge (VGS = 4.5 V) Gate-to-Source Charge Gate-to-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Continuous Source Current (Body Diode Fig.16) Pulse Source Current (Body Diode) Forward On-Voltage Forward Turn-On Time Reverse Recovery Charge (IS = 12 A, VGS = 0 V) (IF = 12 A, VGS = 0 V, di/dt = 100A/s) Integral pn-diode in MOSFET ISM VSD trr Qrr 25 31 Fig.6 1.0 38 46 A V ns nC (VDS = 15 V, ID = 12 A) (Note 6) Fig.15 (Note 5) Dynamic Characteristics (VDS = 15 V, VGS = 0 V, f = 1.0 MHz) Fig.14 Ciss Coss Crss Qg Qg Qgs Qgd Resistive Switching Characteristics (VDD = 15 V, ID = 12 A, VGS = 10 V, RG = 1.0) (Note 6) (VDD = 15 V, ID = 12 A, VGS = 4.5V, RG = 1.0) (Note 6) td(on) tr td(off) tf td(on) tr td(off) tf IS 10 3.4 36 6.0 16 7.2 34 14 50 ns ns ns ns ns ns ns ns A 1520 314 152 27.9 14 4.9 4.3 35 19 pF pF pF nC nC nC nC gFS (Note 5) RDS(on) 10.8 15.4 28 S 12.5 m VGS(th) 1.0 3.0 V IGSS -100 nA IGSS IDSS 1 10 100 nA A G VDSS/TJ 27 mV/J VDSS 30 V Symbol Min Typ Max Units Source-Drain Diode Characteristics 2004/05/24 Preliminary Champion Microelectronic Corporation Page 2 CMT60N03 N-CHANNEL Logic Level Power MOSFET Note 1: TJ = +25J to 150J Note 2: Current is calculated based upon maximum allowable junction temperature. Package current limitation is 30A. Note 3: Repetitive rating; pulse width limited by maximum junction temperature. Note 4: ISD = 12.0A, di/dt 100A/s, VDD BVDSS, TJ = +150J Note 5: Pulse width 250s; duty cycle 2% Note 6: Essentially independent of operating temerpature. 2004/05/24 Preliminary Champion Microelectronic Corporation Page 3 CMT60N03 N-CHANNEL Logic Level Power MOSFET Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case 1.00 Duty Cycle 50% 20% 10% PDM ZJC, Thermal Impedance 0.10 5% 2% 1% single pulse t1 t2 NOTES: DUTY FACTOR: D=t1/t2 PEAK TJ=PDM x ZJC x RJC+TC 0.01 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 tp, Rectangular Pulse Duration (Seconds) Figure 2. Maximum Power Dissipation vs Case Temperature 60 35 Figure 3. Maximum Continuous Drain Current vs Case Temperature PD, Power Dissipation (W) ID, Drain Current (A) 50 40 30 20 10 0 25 50 75 100 125 150 30 25 20 15 10 5 0 25 50 75 100 125 150 TC, Case Temperature (oC) TC, Case Temperature (oC) Figure 4. Typical Output Characteristics 100 90 VGS = 10V Figure 5. Typical Drain-to-Source ON Resistance vs Gate Voltage and Drain Current 0.10 0.09 ID = 7A ID = 14 A ID = 28 A ID = 55 A RDS(ON), Drain-to-Source ID, Drain Current (A) 80 70 60 50 40 30 20 10 0 0 5 PULSE DURATION = 250 S DUTY CYCLE = 0.5% MAX o TC = 25 C VGS = 4.5V 0.08 ON Resistance () 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 PULSE DURATION = 250 S DUTY CYCLE = 0.5% MAX TC = 25 oC VGS = 4.0V VGS = 3.7V VGS = 3.5V VGS = 3.3V VGS = 3.0V VGS = 2.7V VGS = 2.5V 10 15 20 2 3 4 5 6 7 8 9 10 VDS, Drain-to-Source Voltage (V) VGS, Gate-to-Source Voltage (V) 2004/05/24 Preliminary Champion Microelectronic Corporation Page 4 CMT60N03 N-CHANNEL Logic Level Power MOSFET Figure 6. Maximum Peak Current Capability 10000 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION FOR TEMPERATURES o ABOVE 25 C DERATE PEAK CURRENT AS FOLLOWS: I = I 25 150 - T C ---------------------125 IDM, Peak Current (A) 1000 100 10 VGS = 10V 1 1E-6 10E-6 100E-6 1E-3 10E-3 100E-3 1E+0 10E+0 tp, Pulse Width (Seconds) Figure 7. Typical Transfer Characteristics 30 Figure 8. Unclamped Inductive Switching Capability 1000 ID, Drain-to-Source Current (A) 25 20 15 10 5 0 1.0 IAS, Avalanche Current (A) PULSE DURATION = 250 S DUTY CYCLE = 0.5% MAX VDS = 15 V If R 0: tAV= (L/R) ln[IASxR)/(1.3BVDSS-VDD)+1] If R= 0: tAV= (LxIAS)/(1.3BVDSS-VDD) R equals total Series resistance of Drain circuit 100 STARTING TJ = 25 oC +150 oC +25 oC -55 oC 10 STARTING TJ = 150 oC 1.5 2.0 2.5 3.0 3.5 4.0 1 1E-6 10E-6 100E-6 1E-3 10E-3 100E-3 VGS, Gate-to-Source Voltage (V) tAV, Time in Avalanche (Seconds) Figure 9. Typical Drain-to-Source ON Resistance vs Drain Current RDS(ON), Drain-to-Source ON Resistance (m) 100 RDS(ON), Drain-to-Source Resistance (Normalized) PULSE DURATION = 10 S DUTY CYCLE = 0.5% MAX TC=25C 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 Figure 10. Typical Drain-to-Source ON Resistance vs Junction Temperature VGS = 4.5V VGS = 10 V PULSE DURATION = 250 S DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 15A 10 0 50 100 150 200 250 300 350 400 -75 -50 -25 0 25 50 75 100 125 150 ID, Drain Current (A) TJ, Junction Temperature (oC) 2004/05/24 Preliminary Champion Microelectronic Corporation Page 5 CMT60N03 N-CHANNEL Logic Level Power MOSFET Figure 11. Typical Breakdown Voltage vs Junction Temperature BVDSS, Drain-to-Source Breakdown Voltage (Normalized) 1.10 Figure 12. Typical Threshold Voltage vs Junction Temperature VGS(TH), Threshold Voltage (Normalized) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -75 -50 -25 0.0 25 50 75 100 125 150 (oC) VGS = VDS, ID = 250 A 1.05 1.00 0.95 0.90 -75 -50 -25 0.0 25 50 75 VGS = 0V ID = 250 A 100 125 150 TJ, Junction Temperature (oC) TJ, Junction Temperature Figure 13. Maximum Forward Bias Safe Operating Area Area 1000 Figure 14. Typical Capacitance vs Drain-to-Source Voltage 10000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD ID, Drain Current (A) C, Capacitance (pF) OPERATION IN THIS AREA MAY BE LIMITED BY R 10 DS(ON) S 100 1 .0 100 S 10 m mS CISS 1000 COSS CRSS 10 TJ = MAX RATED, TC = 25 oC Single Pulse DC S 1 1 10 100 100 0.01 0.1 1 10 100 VDS, Drain-to-Source Voltage (V) VDS, Drain Voltage (V) Figure 15. Typical Gate Charge vs Gate-to-Source Voltage VGS, Gate-to-Source Voltage (V) IDR, Reverse Drain Current (A) 12 10 8 6 4 2 0 0 24 6 8 10 12 14 16 18 20 22 24 26 28 30 VDS = 15V ID = 12A Figure 16. Typical Body Diode Transfer Characteristics 180 160 140 120 100 VGS = 0V 80 60 40 20 0 15 0 o C 25 o C -55 o C 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 QG , Total Gate Charge (nC) VSD, Source-to-Drain Voltage (V) 2004/05/24 Preliminary Champion Microelectronic Corporation Page 6 CMT60N03 N-CHANNEL Logic Level Power MOSFET PACKAGE DIMENSION TO-252 B R C E PIN 1: GATE PIN 2: DRAIN PIN 3: SOURCE V 4 1 2 3 K S A U L G J H D TO-263 B C E V PIN 1: GATE PIN 2: DRAIN PIN 3: SOURCE 1 23 S K G J D H 2004/05/24 Preliminary A Champion Microelectronic Corporation Page 7 CMT60N03 N-CHANNEL Logic Level Power MOSFET IMPORTANT NOTICE Champion Microelectronic Corporation (CMC) reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. A few applications using integrated circuit products may involve potential risks of death, personal injury, or severe property or environmental damage. CMC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. customer should provide adequate design and operating safeguards. Use of CMC products in such applications is understood to be fully at the risk of the customer. In order to minimize risks associated with the customer's applications, the HsinChu Headquarter 5F-1, No. 11, Park Avenue II, Science-Based Industrial Park, HsinChu City, Taiwan T E L : +886-3-567 9979 F A X : +886-3-567 9909 Sales & Marketing 11F, No. 306-3, SEC. 1, Ta Tung Road, Hsichih, Taipei Hsien 221, Taiwan T E L : +886-2-8692 1591 F A X : +886-2-8692 1596 2004/05/24 Preliminary Champion Microelectronic Corporation Page 8 |
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